View A3942_7496141.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the A3942 is a highly-integrated gate driver ic that can drive up to four n-channel mosfets in a high-side configuration. the device is designed to withstand the harsh environmental conditions and high reliability standards of automotive applications. serial peripheral interface (spi) compatibility makes the device easily integrated into existing applications. the mosfets in such applications are typically used to drive gasoline or diesel engine management actuators, transmission actuators, body control actuators and other general-purpose automotive or industrial loads. in particular, the A3942 is suited for driving glow plugs, valves, solenoids, and other inductive loads in engine management and transmission systems. the device is available in a 38-lead thin (1.20 mm maximum overall height) tssop package with six pins that are fused internally to provide enhanced thermal dissipation (package lg). it is lead (pb) free with 100% matte tin leadframe plating. 3942-ds, rev. 5 features and benefits ? drives four n-channel high-side mosfets ? charge pump for 100% duty cycle operation ? serial and discrete inputs ? spi port for control and fault diagnostics ? 4.5 to 60 v input voltage range ? sleep function for minimum power drain ? thin profile 38-lead tssop with internally fused leads for enhanced thermal dissipation ? lead (pb) free ? device protection features: ? short-to-ground detection (latched) ? short-to-battery protection (latched) ? open load detection (latched) ? v dd undervoltage lockout ? v cp undervoltage lockout ? thermal monitor quad high-side gate driver for automotive applications package: 38 pin tssop (suffix lg) typical application A3942 approximate scale 1:1 faultz v bat A3942 sdo system control logic sdi csz sclk resetz enb in1 in2 in3 in4 gnd gnd gnd gnd gnd gnd cp1 cp2 cp3 cp4 iref vreg vbb vdd v dd vcp d1 g1 s1 d2 g2 s2 d3 g3 s3 d4 g4 s4
quad high-side gate driver for automotive applications A3942 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating units vbb, cp1, cp3 pins voltage ?0.3 to 60 v dx (drain detect) pins voltage v dx v bb ? 6 v to v bb + 0.5 v v sx (output source) pins voltage v sx ?10 to 60 v vcp, cp2, cp4, gx pins voltage ?0.3 to 74 v all other pins ?0.3 to 7 v operating ambient temperature t a range k ?40 to 125 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc esd rating, human body model aec-q100-002, all pins 2500 v esd rating, charged device model aec-q100-011, all pins 1050 v *with respect to ground. exceeding maximum ratings may cause permanent damage. correct operation is not guaranteed when absolut e maximum conditions are applied. selection guide part number packing A3942klgtr-t 4000 pieces per reel thermal characteristics characteristic symbol test conditions* rating units package thermal resistance, junction to ambient r ja 4-layer pcb based on jedec standard, with no thermal vias 47 oc/w *for additional information, refer to the allegro website.
quad high-side gate driver for automotive applications A3942 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com cbb2 in4 in3 in2 in1 resetz enb csz sclk sdi sdo control logic fault monitor faultz vcp cp4 cp3 cp2 cp1 charge pump v cp uvlo high side driver ccp vbb dx gx sx gnd one of four high-side drivers v cp open load detect v ds monitor reference current vdd rdx l l v dd uvlo creg qx vreg internal regulator thermal warning iref cbb1 cdd v dd c12 c34 voltage to vbb pin and to qx mosfets must come from the same supply cref 60.4 k u v l o gnd gnd gnd gnd gnd rgx functional block diagram name suitable characteristics representative device c12, c34 0.33 f or 0.47 f, 25 v, x7r ceramic cbb1 47 f, 63 v, electrolytic egxe630ell470mjc5s cbb2 0.22 f, 100 v, x7r ceramic ccp 1 f, 16v, x7r ceramic cdd 0.47 f, 16 v, x7r ceramic cref 47 pf, 16 v, x7r ceramic creg 0.22 f, 16 v, x7r ceramic
quad high-side gate driver for automotive applications A3942 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristics symbol test conditions min. typ. max. units supplies and regulators operating voltage v bb 4.5 ? 60 v quiescent current i bb(q) charge pump on, outputs disabled v bb = 60 v ? ? 10 ma v bb = 36 v ? ? 8 ma sleep mode v bb = 36 v ? ? 15 a v bb = 36 v, t j = 25c ? ? 1 a logic supply (voltage supplied to logic circuits) v dd 3 ? 5.5 v logic supply current i dd v dd = 5.5 v, serial port switching ? ? 3 ma v dd = 5.5 v, device quiescent or in sleep mode ? ? 0.5 ma logic supply uvlo threshold v dd(uv) v dd falling, faultz pin held active (low) for 1.5 v v dd v dduv 2.6 ? 2.9 v logic supply uvlo hysteresis v dd(hys) 100 150 200 mv charge pump switching frequency f cp ? 100 ? khz charge pump output voltage v cp measured relative to vbb pin v bb = 12 v, i cp = 10 ma 10 ? 13 v v bb = 6.0 v, i cp = 5 ma 10 ? 13 v v bb = 4.5 v, i cp = 5 ma 7 ? 11 v charge pump uvlo v cp(uv) relative to vbb pin, v cp falling 5.1 ? 5.8 v internal regulator voltage v reg creg = 0.22 f ?4?v regulator voltage uvlo v reg(uv) v reg falling 3 ? 3.8 v regulator voltage uvlo hysteresis v reg(hys) 100 ? 400 mv control circuits current reference source voltage v ref 1.14 1.2 1.26 v master reset pulse t reset resetz pin pulsed low 0.3 ? 5 s sleep command t sleep resetz pin held low 20 ? ? s wake-up delay t wake resetz pin held high; ccp = 1 f ??2ms logic i/o logic input voltage, high v ih 0.7 v dd ?v dd v logic input voltage, low v il 0? 0.3 v dd v electrical characteristics valid at ?40c t j 150c, c12 = c34 = 0.47 f, ccp = 1 f, r ref = 60.4 k , and v bb within limits, unless otherwise noted continued on the next page...
quad high-side gate driver for automotive applications A3942 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristics symbol test conditions min. typ. max. units logic input hysteresis v hys 0.1 v dd ??v logic input current 1 i i(hi) csz pin v i = v dd = 5.5 v ??10 a sdi and sclk pins ? ? 5 a all other pins ? ? 100 a i i(lo) csz pin v i = 0 v ? ? ?100 a sdi and sclk pins ? ? ?5 a all other pins ? ? ?10 a logic output voltage, sdo pin (cmos push-pull circuit) v out(hi) i out = ?1 ma v dd ? 0.5 ?v dd v v out(lo) i out = 1 ma ? ? 0.4 v faultz pin active (low) voltage v faultz(lo) i faultz = 1 ma, v dd = 1.5 v, v bb = 4.5 v ? ? 0.4 v faultz pin inactive (high) current i faultz(hi) v faultz = 5 v ? ? 10 a drivers gate voltage, high v g(hi) measured relative to sx pin, capacitive load?fully charged v cp ? 1 ?v cp v gate voltage, low v g(lo) measured relative to sx pin, capacitive load?fully discharged ? ? 0.1 v peak gate current 1,2 i g(hi) r g = 0 , 1 v v gs 4 v, v sx = v bb v bb = 4.5 v, v cp = 9 v ?10 ? ? ma v bb 9 v, v cp = 13 v ?15 ? ? ma i g(lo) r g = 0 , v gs = 1 v, v sx = 0 v 10 ? ? ma r g = 0 , 2 v v gs 4 v, v sx = 0 v 25 ? ? ma propagation delay t p(on) from 90% v inx to v gx ? v sx = 200 mv ? 0.6 ? s t p(off) from 10% v inx to v cp ? v gx = 200 mv ? 0.6 ? s gate-to-source resistance r gs resetz pin held low; v gsz = 10 v 300 500 800 k gate-to-source zener diode voltage v gs(z) i g = 2 ma 15 ? 18 v drain leakage current i dlkg resetz pin held low, v bb = v dx = 60 v ? ? 10 a resetz pin held low, v bb = v dx = 36 v t j = 150c ? ? 5 a t j = 25c ? ? 1 a electrical characteristics (continued) valid at ?40c t j 150c, c12 = c34 = 0.47 f, ccp = 1 f, r ref = 60.4 k , and v bb within limits, unless otherwise noted continued on the next page...
quad high-side gate driver for automotive applications A3942 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristics symbol test conditions min. typ. max. units driver fault detection drain fault detect current i dx v bb = 60 v 75 100 125 a v bb = 36 v 85 100 120 a drain fault detect voltage 3 v dx v bb 9 v v bb ? 3 ? v bb + 0.2 v v bb = 6 v 5 ? v bb + 0.2 v v bb = 4.5 v 4 ? v bb + 0.2 v open load detect source current 1 i ol v sx = 1.35 v; 4.5 v v bb 36 v ?48 ? ?82 a open load detect voltage v ol 1.4 1.5 1.6 v open load v sx clamp v clamp active (when an open load fault is active), v bb 36 v ??5v i clamp current limit in short-to-battery; v sx =v bb = 36 v ? ? 200 a turn-on blank time t on(00) t on(00) is the default, t j = 150c 2.5 ? 3.4 s t on(01) 3.7 ? 5.9 s t on(10) 5.6 ? 11.2 s t on(11) 8.9 ? 22.3 s turn-off blank time t off ?t on ? s short-to-ground fault detect filter delay t stg from v sx < v dx to 90% v faultz ? 1 1.2 s stb comparator offset voltage v os(stb) ? ? 60 mv stg comparator offset voltage v os(stg) ? ? 45 mv temperature monitor thermal warning threshold 4 t warn temperature rising 155 165 175 c thermal warning hysteresis t warn(hys) ?15? c 1 for input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. 2 for i g(hi) , v cp relative to v bb . 3 minimum values of v dx are specified only to avoid short-to-battery nuisance faults. for more information, refer to the open load fault level topic i n the applications information section. 4 minimum and maximum not tested; guaranteed by design. electrical characteristics (continued) valid at ?40c t j 150c, c12 = c34 = 0.47 f, ccp = 1 f, r ref = 60.4 k , and v bb within limits, unless otherwise noted
quad high-side gate driver for automotive applications A3942 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristics symbol test conditions min. typ. max. units transfer frequency f ? ? 8 mhz setup lead time t lead 375 ? ? ns setup lag time t lag 50 ? ? ns setup time before read t su 15 ? ? ns access time before write t a c sdo = 100 pf ? ? 340 ns chip selection inactive time t cszn 2?? s delay before output disabled t dis c sdo = 0 pf ? ? 100 ns serial clock period t sclk 125 ? ? ns serial clock pulse width, high t w(hi) 50 ? ? ns serial clock pulse width, low t w(lo) 50 ? ? ns serial clock hold time t h(sclk) 300 ? ? ns serial data in hold time t h(sdi) 20 ? ? ns serial data out hold time t h(sdo) c sdo = 0 pf 0 ? ? ns serial data out time before valid state t vs c sdo = 100 pf, v dd = 3 v ? ? 120 ns c sdo = 100 pf, v dd = 4.75 v ? ? 80 ns serial peripheral interface (spi) timing characteristics valid at ?40c t j 150c and v bb and v dd within limits, unless otherwise noted
quad high-side gate driver for automotive applications A3942 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dx vbb 8 v gx sx v cp open load v ds delay gx off gx on gx on gx off gx on gx off logic faultz system and load faults sport osc serial port mask clear read i ol vbb i dx short to ground short to battery r gs r dx l o a d write vclamp v ol r gx d7 sclk csz sdi sdo t lead hi-z t a d7 d6 d6 t w(hi) t w(lo) t sclk t vs t h(sdi) t h(sclk) t lag t su t dis t cszn d0 d0 don?t care t h(sdo) serial peripheral interface (spi) timing diagram fault system block diagram
quad high-side gate driver for automotive applications A3942 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com inx i gx gate begins to charge v sx timer is running for turn-on blank time set blank time to expire after v sx nears v bb v gsx timer is running for turn-off blank time t p(off) t p(on) v gs = v th v bb set blank time to expire after v sx nears 0 v input settingstiming chart fault logic table circled data cells indicate default settings, x indicates ?don?t care?, z indicates high impedance state causes effects mode of operation resetz enb vdd uvlo vcp uvlo channel-specific thermal warning faultz gx vcp vreg open load short-to-battery short-to-ground off-state faults masked 1000000x01011 gates actively pulled low 1100000x01inx11 normal operation 1100000x10inx11faultz issued but A3942 fully operational 1100xx0101inx11 normal operation, ol and stb masked 1x00001xx0011 stg cannot be masked 1x000100x0011stb 1x001000x0011ol 1 x 0 1 x x x x x 0 0 uv 1 vcp uvlo disables outputs only 1 x 1 0 x x x x x 0 0 1 1 vdd uvlo disables outputs only 0xxxxxxxx0z0 0 sleep mode
quad high-side gate driver for automotive applications A3942 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com serial port bit definition all bits active high, except writez register bits d7 d6 d5 d4 d3 d2 d1 d0 input address msb address lsb input read enable mask off-state faults (*) clear faults stg blank time msb stg blank time lsb gate on/off output fault address msb address lsb writez charge pump uvlo thermal warning open load fault (*) stb fault (*) stg fault serial port registers description there are two 8-bit registers served by the serial port, the input register and the output fault register. the structure of the registers is shown in the table at the bottom of this page. the function of each bit in the registers is described in this section. input register d0 gate on/off bit this bit is used to control the gate drive output. it is logically ored with the signal on the discrete input pin, inx, corresponding to each of the four channels, according to the following table: ored settings result on gx pin bit d0 pin inx 0 0 off 01on 10on 11on d1, d2 short-to-ground (stg) turn-on blank time msb and lsb bits the blank time, t on(xx) , delay allows switching transients to settle before the A3942 stg function checks for a short. for each individual channel, the combination of these bits sets the wait time for the v ds monitor, according to the following table: d2 d1 t on selected 00 t on(00) * 01 t on(01) 10 t on(10) 11 t on(11) *default state at device power-on d3 clear faults bit this bit is used to clear a latched fault. after the fault is cleared, the gate output can again follow the input logic to determine if the fault is still present. faults are cleared on a channel specific basis. d4 mask off-state faults bit [see asterisks (*) in the table below.] when the application requires that short-to-battery (stb) and open load (ol) faults be checked primarily before output is enabled for the first time, this bit can be used to allow stb and open load faults to be ignored during normal operation (short-to- ground faults can not be masked). this bit is applied
quad high-side gate driver for automotive applications A3942 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com on a channel-specific basis, according to the following table: d4 setting handling of off-state faults 0 registered 1 ignored d5 read enable bit this bit enables or disables read- ing on the serial inputs, according to the following table: d5 setting handling of serial input 0 ignored 1 registered d6, d7 address msb and lsb bits (input and out- put fault registers) for channel-specific bits, these bits are used to specify which channel is indicated. the channel-specific bits are: register channel-specific bits input d0, d1, d2, d3, d4 output d0, d1, d2 these bits determine the channel, according to the fol- lowing table: d7 d6 channel selected 00 1 01 2 10 3 11 4 output fault register d0 short-to-ground (stg) fault bit the voltage from drain to source for each mosfet is monitored. an internal current source sinks i dx from the dx pins to set the v ds threshold for each channel, the level at which an stg fault condition is evaluated. the A3942 enables monitoring for an stg fault after the mosfet is turned on and the turn-on blank time, t on , expires. (the mosfet is turned on via the input register d0 bit, ored with the inx discrete input pin for the channel of the mosfet, and t on is set by input register d1 and d2 bits). if the mosfet gate- to-source voltage exceeds the v ds threshold, then an stg fault will be registered for that channel, the mosfet gate will be discharged, and the faultz pin will be set low (active). an stg fault is latched until cleared (using the input register d3 bit). in the meantime, the other channels can continue to operate normally. d1 short to battery (stb) fault bit when a chan- nel turns off, stb fault detection is blanked for t off . subsequently, if the sx pin voltage exceeds the v ds threshold voltage for that channel, an stb fault is latched. the output for that channel is disabled until the fault is either cleared (via the input register d3 bit) or the off-state fault diagnostics are masked (via the input register d4 bit). because the output is disabled, there is no active pull-down during an stb event. note that, in general, when the voltage on sx is high enough to trip the stb comparator, it also trips the ol comparator, and both the stb and the ol faults are latched. d2 open load (ol) fault bit when a channel turns off, the ol fault is blanked for t off . a small bias current, i ol , is sourced to the sx pin of the channel. there it divides between rsx and the load. if the load is open, the sx voltage will rise above the ol fault detection threshold. in that case, the output is disabled until the fault is cleared (via the input register d3 bit) or the off-state fault diagnostics are masked (via the input register d4 bit). d3 thermal warning bit a die temperature monitor is integrated on the A3942 chip. if the die temperature
quad high-side gate driver for automotive applications A3942 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com approaches the maximum allowable level, a thermal warning signal will be triggered. note that this fault sets the faultz pin low (active), but does not disable the outputs or operation of the chip. d4 charge pump uvlo bit the charge pump must maintain a voltage guard band above v bb , in order to charge the gates when commanded to turn on the mosfets. if an undervoltage (uvlo) condition is detected on the charge pump, the faultz pin will be set low (active), and all outputs will be disabled. d5 writez (not write) bit in a written byte, d5 = 0. d6, d7 address bits see description, above. pin descriptions in this section, the functions of the individual termi- nals of the A3942 are described. vbb supply voltage (power) the A3942 is fully operational over the specified range of v bb . the exter- nal mosfets must be supplied by the same voltage source as the A3942. a bypass capacitor should be placed as close as practicable to the A3942. vdd supply voltage (logic) logic voltage must be supplied to the A3942. the wide allowable range of input voltages allows both 3.3 v and 5 v supplies. a bypass capacitor should be placed as close as practi- cable to the A3942. vcp charge pump the integrated charge pump is used to generate a supply above v bb to drive the gates of the external power mosfets. this tripler keeps the part functional over a wide range of v bb . cp1 through cp4 charge pump capacitor con- nections these are the connections for the two exter- nal capacitors that level-shift the charge up to v cp . vreg internal linear voltage regulator this pro- vides a connection for an external capacitor that sets the regulation value for voltage supplied to internal logic circuits. in1 through in4 discrete inputs for each output channel, the gate pin, gx, sources voltage when the corresponding inx pin is set high. gx sinks voltage to ground when the corresponding inx pin is set low. the inx setting is logically ored with the gate on/off bit (input register bit d0) for the respective output. d1 through d4 output drains for each output chan- nel, the voltage on the corresponding dx pin is used to evaluate stb and stg fault conditions. the A3942 compares the dx voltage level to the v ds threshold of the mosfet to determine if a fault condition exists. the trip voltage level is set by selecting an appropriate value for the resistor, rdx, connected to the corre- sponding current sink. because both the dx pins and rdx are high impedance, each rdx must be placed as close to the corresponding A3942 dx pin as practi- cable. g1 through g4 output gates these pins drive the gates of the high-side external mosfets. they source voltage from vcp and sink to gnd. the correspond- ing external gate resistors, rgx, should be 2 k for consistent switching times between A3942s when applicable (see i g(hi) and i g(lo) in the electrical char- acteristics table). if negative voltages are applied, gx is clamped to gnd by internal diodes. back-to-back zener diodes are internally connected between gx and sx. sx output sources these are used to measure the source terminal of the external mosfet. the pins may be tied directly to the mosfet. although the sx pins can survive large negative transients, it is recom- mended to connect a clamp diode between the sx pin and ground to limit any negative transients at the sx pin when a load is switched off. this helps to avoid false fault detection caused by transient noise coupling into adjacent channels which may not be switching and therefore have no fault blanking during the tran- sient. this is especially recommended when there is significant wiring between the load and the sx pin even if the load incorporates a recirculation diode.
quad high-side gate driver for automotive applications A3942 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com resetz master reset and sleep mode pulsing this pin low clears all latched faults in the channel-specific fault registers. it also clears the serial port registers (they return to their default values). when resetz is held low long enough (t > t sleep ) the A3942 goes to sleep, as described in the sleep topic in the functional description section. enb enable set low to actively pull low all outputs. faultz fault active low open drain output. signals a fault. allows parallel connection with faultz sig- nals from other devices when required. sclk spi clock see serial port operation topic in functional description section. csz spi chip select input. sdo spi data output connection. sdi spi data input connection. iref current reference defines the current used as a reference to set gate drive currents, diagnostic currents and internal timers. a resistor, rref, con- nected between the iref pin and the adjacent gnd pin is selected to set the reference current to 20 a. the iref pin is a voltage source at a voltage, v ref , of typically 1.2v. the resistor required is therefore 60.4kohm, which is the standard resistor value that provides a typical current closest to the 20 a target. any variation in rref will affect the internal settings as described in the section below on rref selection. being a high impedance node, the iref pin is suscep- tible to external sources of noise and transients and should be decoupled with a capacitor across rref between the iref pin and the adjacent gnd pin. the capacitor value should be less than 100pf to avoid any delay when power is first applied to the A3942 or when coming out of sleep mode. when control- ling large load currents a larger capacitor may be required to suppress any transient noise. at power-on or when coming out of sleep mode this capacitor will be charged at typically 240 a until it reaches v ref . the time taken to charge the capacitor will be approxi- mately: t charge = 5 c where t charge is in s and c is the capacitor value in nf. at least twice this time should be allowed, after power-on or after coming out of sleep mode, before the A3942 is used to switch any loads. gnd ground all gnd pins are internally fused to the metal die pad to which the chip is soldered. this allows for high thermal conductance through the gnd pins. connecting to these pins to a pcb ground plane improves thermal performance. functional description power on when power is applied to either vdd or vbb, the output fault register is initially loaded with default values, all zeros (0). however, as individual internal circuits are initially powered on, they may latch spurious faults in the fault registers for each channel. therefore, before operating the A3942 all fault registers must be cleared by pulsing the resetz pin. sleep mode this mode disables various internal cir- cuits including the charge pump, vreg, and the logic circuits. the serial port also is disabled. all input and output fault register bits are cleared. to leave sleep mode, pull resetz high and then allow a delay for the charge pump to stabilize. before sending commands, clear any spurious faults as described in the power on topic. faults faults are categorized either as system faults or load faults . all faults are ored to the faultz pin. system faults are vreg uvlo, cp uvlo, vdd uvlo, and thermal warning. they are not latched in the channel-specific self-protection circuit fault reg- isters, however, the flags in the output fault register
quad high-side gate driver for automotive applications A3942 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com bits d3, d4, and d5, are latched. if the fault condition is resolved, these flags are latched until they are read, at which time they are cleared. load faults are ol, stb, and stg. they are latched into the channel-specific self-protection circuit fault registers, and shifted into output fault register bits d0, d1, and d2 when called. thus, load faults may be masked or cleared on a channel-specific basis. serial port operation the serial port is compatible with the full duplex serial peripheral interface (spi) conventions. the inputs to the spi port are logically ored with the discrete input pins, inx, settings. this allows indepen- dent operation using only the discrete inputs, only the serial inputs, or both. timing is clocked by an on- board 4 mhz oscillator. when a chip select event occurs, the output fault register loads one eight-bit byte into the shift register, and the byte is then shifted out through the sdo pin. simultaneously, bits at the sdi pin are shifted into the shift register (full duplex). at the end of a chip select event, the shift register contents are latched into the input register. alternative configurations multiple A3942s can be configured together. ? standalone connection in this configuration, the master simultaneously shifts eight bits in through the sdi pin and shifts eight bits out of the sdo pin. first, the csz pin is set low. then, the output fault register is loaded with the relevant fault byte (see the output fault register topic below). eight clock cycles are used to perform the shifts. ? parallel connection because each slave has a csz pin, operation is identical to the standalone configu- ration. when csz is inactive, sdi is ?don?t care? and sdo is high impedance. ? daisy chain connection the master shifts n bytes (eight bits each) during n 8 clock cycles. regard- less of the position of an individual A3942 slave in the daisy chain, the slaves shift the output byte during the first eight clock cycles after csz goes low. when csz goes high, the eight bits in the shift register are latched into the input register. serial port disabling disable the serial port by set- ting the csz pin high while in sleep mode. this loads the input register with default values, all zeroes (0). serial port error handling input data is discarded if the number of bits in an input stream are not a mul- tiple of eight. furthermore, unless the number of clock cycles is a multiple of eight while csz is active, any bits shifted in from the sdi pin are discarded. input register operation after a valid byte is latched into the input register from the shift register, bit d5 is evaluated to determine if the byte is to be read. an inactive (0) bit value causes all other bits to be ignored. if bit d5 is active (1) the other bits are read and decoded. bits d6 and d7 are used to determine which output channel is updated. bits d0 through d4 set the channel-specific operation, including clearing and masking of faults. output fault register operation this register is loaded with fault data to be shifted out through the sdo pin. no handshaking is required. the output fault register contains data on active faults. four internal channel-specific fault registers contain any latched fault data for each respective channel. the following describes how the A3942 determines which channel-specific fault register to transfer into the output fault register. ? no faults if there are no current faults, the output fault register is loaded with all zeros: 0 0 0 0 0 0 0 0
quad high-side gate driver for automotive applications A3942 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ? single fault if there is only one fault detected, the output fault register is filled to indicate that fault. for a load fault, the address bits are set to indicate the affected channel; for example, a short-to-battery on channel 3 would be written: 1 0 0 0 0 0 1 0 on the other hand, for system faults, the address bits are irrelevant, and a cp uvlo fault would be loaded as: 0 0 0 1 0 0 0 0 with the address bits defaulting to 0 0 . ? multiple system faults if there are multiple system faults, the output fault register is loaded with the setting for each system fault (the address bits re- main irrelevant, as in the case of a single fault). for example, when cp uvlo and thermal warning faults both have occurred, the output fault register is loaded with: 0 0 0 1 1 0 0 0 ? multiple system faults and single channel load fault if one or more system faults and one or more load faults from a single channel have occurred, all faults are loaded into the output fault register, with the channel of the load faults indicated in the address bits. for example, a cp uvlo system fault and an stg load fault on channel 2 would be written as: 0 1 0 1 0 0 0 1 ? multiple channel load faults when load faults occur on more than one channel, the data cannot be signalled in a single sdo byte. however, the data can still be retrieved. the A3942 polls each channel- specific fault register, in ascending order by channel number. each output is delimited by the appropriate csz event. for example, assume an ol on channel 2 and an stg on channel 4. the first csz event writes: 0 1 0 0 0 1 0 0 and the second csz writes: 1 1 0 0 0 0 0 1 in summary, all faults are retrieved by issuing con- secutive csz events until the channel number stops increasing. ? if there are no faults, this byte will be shifted out each time: 0 0 0 0 0 0 0 0 ? if there are only system faults, this byte will be shifted out each time: 0 0 [1|0] [1|0] [1|0] 0 0 0 ? if there are system faults and only one load fault, one byte contains all of the fault data. ? if there are load faults on more than one channel, these bytes would be shifted out in succession, and any existing system faults will be indicated. for ex- ample, if there were no system faults and load faults on channels 2, 3, and 4, the following series of bytes would be shifted out: 0 1 0 0 0 [1|0] [1|0] [1|0] 1 0 0 0 0 [1|0] [1|0] [1|0] 1 1 0 0 0 [1|0] [1|0] [1|0] 0 1 0 0 0 [1|0] [1|0] [1|0] . . . applications unused outputs when any of the four output chan- nels are not used, the related pins should be connected as follows: unused channel pin connection inx gnd sx gnd dx vbb gx floating rref selection the tolerance on rref can be as high as 4%. depending on how a specific part
quad high-side gate driver for automotive applications A3942 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com changes over temperature changes and lifetime, the 4% range generally covers nominal 1% resistors. the parameters which are affected by changes in rref are listed in the following table: parameter change as rref tolerance increases decreases i ref ?+ t reset +? t sleep +? t wake +? i g(hi) and i g(lo) ?+ i ol ?+ t on and t off +? setting fault circuit trip levels the load faults, short-to-battery (stb), short-to-ground (stg), and open load (ol), are all latched. the thresholds for stg and ol faults can be set by the value for the rdx resistor. open load fault level when the gate is commanded off, a commanded current, i ol , is sourced to sx to detect if the load is still in the circuit. v ol is compared to i ol [ r l // r gs ] to evaluate an ol fault. if the load has been removed, v sx exceeds v ol and a fault is registered. v sx would drift to v bb when an open load exists and thereby inadvertantly trip a nui- sance stb fault. to prevent this, the sx pin is clamped to v clamp . the operating limits specified in the electrical char- acteristics table allow the fault circuitry to distinguish all faults within the operating range of v bb . if, how- ever, the specified limits on v dx are too restrictive at low v bb levels, the only repercussion is a nuisance stb fault, and this only occurs when an ol condi- tion exists. the limit on v dx can be ignored either if the off-state faults are masked or if it is acceptable to latch the nuisance fault and clear it when the ol fault is cleared. because v os << v ol , a fault is registered if i ol r l // r gs > v ol . hence, the trip level, r l (trip) is: r l (trip) ? 1 v ol i ol r gs 1 = ? ? ? ? ? ? ? ? ? the ol circuit and its tolerances are designed to ensure that external loads above 50 k are identified as open load and that loads below 10 k are identified as valid. note that these numbers are valid in steady state. as a result, blanking times must be set appropri- ately for a given load. under normal conditions, when the external mosfet is off, and the load is in circuit, i ol r l < v ol . short-to-battery fault level the stb comparator compares the load voltage i ol r l // r gs ] to the voltage set by rdx, v bb ? i d r d . the comparator is active only when the gate is com- manded off. during an stb condition, i ol = 0 because the current source has run out of headroom. a fault is registered when v l > v bb ? i d r d v os.
quad high-side gate driver for automotive applications A3942 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com that is, the load voltage is within ? v = i d r d volts of v bb . using v ds = v bb ? v l and rearranging, we find that v ds < i d r d v os . therefore, r d = ( v ds (trip) v os ) / i d , which is also the case for stg faults, described below. note that an stb condition generally latches the ol flag as well. under normal conditions r l << rgs and i ol flows through the load, given i ol ( r d + r l ) < v bb ? i d r d v os . because i ol ( r d + r l ) 0 when the external mosfet is off, no fault is registered. short-to-ground fault level the effect of the stg comparator is to compare the external mosfet v ds (v l ) to the set trip voltage v bb ? i d r d . the comparator is active only when the gate is com- manded on. also, the sourced current i ol is deacti- vated. if v ds is too large, an stg fault is registered when v l < v bb ? i d r d v os , or, because the external mosfet v ds = v bb ? v l , v ds > i d r d v os . therefore, the stg trip level in the on state is the same as the stb level in the off state: r d = ( v ds (trip) v os ) / i d . converse to the preceding, in normal operation v l > v bb ? i d r d v os , or v ds < i d r d v os . power limits power dissipation, p d , is limited by thermal con- straints. the maximum junction temperature, t j (max), and the thermal resistance, r ja , are given in this datasheet. the maximum allowed power is then found for a given ambient, t a , from this equation: t j = p d r ja + t a , or p d = ( t j ? t a ) / r ja . the three main contributions to power dissipation are: ? quiescent supply, p bb(q) ? driver outputs, p drv , and ? logic level supply, p dd . these three terms appear in the following equation: p d = p bb(q) + p drv + p dd . the quiescent supply current leads to a baseline power loss: p bb(q) = v bb i bb(q) . in general, the losses in a driver can be quantified as follows. given that the driver current leaves gx to charge a gate, and assuming that the external circuit is approximately lossless, then the same charge is sunk back into gx. therefore, all driver current can be treated as going to heat the chip. total current into v bb includes the quiescent current, i bb(q) , plus additional current, ? i bb , to energize the gates. the latter is three times the average gate cur- rent: ? i bb = 3 i gx (av) . the average load current is calculated using the gate charge, q g , from the external mosfet datasheet and the switching frequency: i gx (av) = f sw q g .
quad high-side gate driver for automotive applications A3942 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com if all four outputs are supplying this current, ? i bb = 4 (3 i gx ) = 12 f sw q g , and p drv = v bb ? i bb = 12 f sw q g v bb . finally, loss in the logic circuits is p dd = v dd i dd . example : find the junction temperature with one irfz44es mosfet at each output, being switched at 5 khz, and given v bb = 14 v and v dd = 5.5 v. answer: the irfz44es datasheet gives q g (max) = 60 nc (note that this parameter depends on circuit design constraints, such as v ds ). the electrical char- acteristics table gives the following maximum values for the A3942: i bb(q) = 10 ma, v dd = 5.5 v, and i dd = 3 ma. first, calculate total power loss: p d = v bb i bb(q) + 12 f sw q g v bb + v dd i dd = 14 v 11 ma + 4 3 5 khz 60 nc 14 v + 5.5 v 3 ma = 221 mw . then, the junction temperature can be found for a given ambient temperature; t a = 125c is assumed here. thermal resistance depends significantly on the board design; r ja = 100 c/w is assumed here. sub- stituting these values: t j = p d r ja + t a = 221 mw 100 c/w + 125c = 147c . layout and components general good practices should be followed. in addi- tion, the following are recommended: ? locate bypass capacitors (vbb, vdd, vreg, and iref) as close to the A3942 as practicable. ? traces to bypass capacitors should be as wide as practicable; minimize the number of vias. ? use both bulk storage capacitors (for example, elec- trolytic) and low impedance bypass capacitors (for example, ceramic) on all supply pins. see the func- tional block diagram for recommended values. ? input and output lines should not be in close proxim- ity. if they do overlap, it should be at right angles. ? use ample copper in the ground and power paths. use planes or fills where possible. ? the A3942 ground and vbb supply should be star- connected to the power ground and supply. ? the trace connecting the rdx resistors to the A3942 dx pins should be as short as possible. ? the trace leaving the other side of the rdx resistors can be long because it has a low impedance path to ground; however, it must run independently to the re- spective external mosfet in order to make a kelvin connection. ? all support capacitors are to be referenced to the A3942 ground plane or ground fill. minimize loop area of traces. ? these traces should be as wide as practicable: vbb, vdd, vreg, vcp, and gx. secondarily, it is also preferred that the traces to the charge pump caps be as wide as practicable. in both cases, the number of vias should be minimized. ? minimize the distance connecting to ground pins in order to minimize ground loops. finally, a note about thermals. because the A3942 ground pins are internally fused to the die mounting pad, they are the main path for heat dissipation. in applications producing high junction temperatures, care must be given to designing the thermal path. for example, multiple thermal vias should be run from ground pins down to the ground plane. if space allows, wide traces from ground pins to exposed copper fills on the top layer efficiently release heat through con- vection cooling.
quad high-side gate driver for automotive applications A3942 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list no. name pin description 1 sdo serial data out 2 sdi serial data in 3 sclk serial clock 4 csz chip select ? not 5 faultz fault ? not (open drain) 6 resetz reset ? not (discrete) 7 enb enable (discrete) 8 vdd logic supply 9 iref current reference pin 10 gnd 11 in2 discrete input channel 2 12 in1 discrete input channel 1 13 d2 channel 2: drain 14 d1 channel 1: drain 15 gnd 16 s1 channel 1: source 17 g1 channel 1: gate 18 g2 channel 2: gate 19 s2 channel 2: source 20 s3 channel 3: source 21 g3 channel 3: gate 22 g4 channel 4: gate 23 s4 channel 4: source 24 gnd 25 d3 channel 3: drain 26 d4 channel 4: drain 27 in3 discrete input channel 3 28 in4 discrete input channel 4 29 vreg internal regulator 30 vbb power supply 31 gnd 32 vcp reservoir capacitor terminal 33 cp1 charge pump capacitor terminal 34 cp3 charge pump capacitor terminal 35 cp2 charge pump capacitor terminal 36 cp4 charge pump capacitor terminal 37 gnd 38 gnd
quad high-side gate driver for automotive applications A3942 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 1.20 max 4o 6.00 1.60 seating plane 0.50 c 0.10 38x c 0.30 0.10 0.05 0.22 0.05 4.40 0.10 6.40 0.20 9.70 0.10 0.15 +0.06 ?0.05 2 1 38 2 1 38 gauge plane seating plane a a terminal #1 mark area all dimensions nominal, not for tooling use (reference jedec mo-153 bd-1) dimensions in millimeters pins 10, 15, 24, 31, 37, and 38 fused internally b b reference pad layout (reference ipc sop50p640x110-38m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances pcb layout reference view 0.50 0.25 copyright ?2008-2010, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com lg package, 38-pin tssop

▲Up To Search▲

Price & Availability of A3942

	To Download A3942 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .